Front side of the original Oval UD-80
Front side of the original Oval UD-80
The left Serial I/O connector is an 8-pin DIN for the PX-8/PX-4, The RGB and Video are the display outputs. The hole at the right is for the Filink mode button.
As previously reported, the 7.11A ROM didn't work properly with the Re-UD-80 because of the video sync signal configuration. The 5.21E ROM used one pin for both horizontal and vertical sync, the 7.11A ROM used two pins. The board can be modified to work with the 7.11A ROM, but not without loosing5.21E compatibility. Adding a jumper would mean a new board version. Instead I attempted to change the configuration of the EF9345 video controller in the 7.11 ROM to match that of the 5.21E ROM. This was successful, resulting in the 7.11c ROM. The ROM image can be found here: ud80_rom7.11composite.zip.
In total three bytes are different between the 7.11A and 7.11c version; the TGS configuration byte, one character of the permanent banner and one of the two checksum bytes:
0E43 - $80 > $90 ; EF9345 TGS register composite sync bit 0F92 - 'A' > 'c' ; main banner character 3FFC - $C9 > $C9 ; checksum high byte 3FFD - $1A > $4C ; checksum low byte
With this result, I think the project is completed. It might be interesting to explore the features of the UD-80, but that has to compete with other planned projects.
The MC6801 instruction set is very pleasant to work with.
Here the re-UD80 in case, right, with a PX-8 attached.
The case is designed to fit around the board with small tolerances. No internal mounting is required when the case is closed.
The board is prepared for the classic 9V DC wall-brick, supplied through a barrel-jack 2.1/5.5mm with pin positive. The regulator has the same pin-out as the LM7805. There is little room for a cooling sink, so a switching regulator is advised.
Power consumption is modest, ~200mA, so it is feasable to power the board directly from a USB charger or power bank. Bridge the outer two pin holes instead of the 7805 and directly connect 5V to the barrel-jack socket.
Initial testing was done with the 5.21 firmware, which has the PX-8 driver programs. This firmware uses the EF9345 Display Processor pin 5 (HVS/HS) for the sync signal. When the 7.11 firmware was used for testing, the vertical sync was missing, resulting in a vertical rolling of the screen. The scope confirmed that the vertical sync is present on pin 6 (PC/VS). This led to the fix described below, which ANDs the two signals to a combined sync. But then the 5.21 stopped producing a screen, as pin 6 is continuously low.
The fix for the 7.11 firmware broke the 5.21 firmware. Looking at photo's of the original board, it seems pin 6 is not connected at all to the video circuit (it goes to a strip of test points, but stops there). My conclusion it that the 7.11 version will not work on the original board (this version at least).
My solution to this problem is adding an extra jumper to be set or un-set when you switch firmware version. This would mean a new version of the board, which I don't like. An other option would be to patch either ROM to match the sync configuration of the other, but I haven't looked seriously at a disassembly yet.
The problem only exists when you want to switch firmware. For either firmware is a
working circuit, but they are not the same.
This is the description of the fix for the 7.11 firmware but will break the 5.21 firmware. An unmodified 0.10 board will work with the 5.21 firmware. With the fix
in place, disconnecting the diode from pin 6 will restore the original situation.
The cathode of the diodes is where the band is (usually black or white). The diodes
I used were BAT83, but most generic small signal schottky diode will probably work.
All the components are finally in and soldered to the new 0.10 board. It was mainly my poor component inventory management and distractions why it took so long.
Before testing the new board, I adapted the old 0.8 prototype to the new video circuit,
and it looks quite good on my preferred display. Good enough to update the DIP-switche table:
1. off = 80 char./line, on = 40 char./line
2. ?
3. off = PAL, on = NTSC
4. off = white on black, on = black on white
5. ?
6. ?
7. ?
8. ?
1. off = NTSC, on = PAL
2-8. ?
The 7.11A version uses the DIP switch only for video mode. At least the 40/80 column mode is moved to software as it is mentioned in the ROM dump. This ROM also contains the intriguing text: "System Utilities Screen".
The 5.21E ROM version configures the EF9345 HS pin for both horizontal sync and vertical sync.
Most connectors are in, and they seem to fit the footprints. The routing in KiCAD is also done and the files are sent to JLC for board manufacturing. It didn't seem easy to cram all components into 10x10cm, for the extra cheap production costs. So I settle for just cheap (less than $8 for 5 boards, instead of less than $2). Shipping still costs more.
The board appears to be stable now, and works with both ROMs for the PX-4 and 8. The main remaining issue is the composite video output, which produces a marginal signal. It works with some vintage analog CRT displays, but not modern stuff. Crashedfiesta showed it is not the timing, it must be signal levels.
But now I want to create a new board, but have to decide on the connectors. The plan now is to have most connectors mounted on the PCB.
Some (blinking) LEDs for power and serial line activity. Push buttons for FILINK mode and RESET.
There appear to be no footprint libraries in KiCAD for the RCA and DIN-8 connector, so that means ordering them first and on arrival design the footprints and create the final PCB. Hopefully the video problem is solved by then.
It could take some months to finish. For the very impatient and ambitious there are some v1.0 boards left, but the fix list is impressive.
With an interim cable, transferring drivers from the UD-80 to the PX-8 finally succeeded.
Filink mode from the Oval UD-80
Filink mode from the PX-8
The final connection I use between the UD-80 and the PX-8 is a #724-F9 and a DE-9 female to header adapter. The DE-9 connector is wired as a loopback. The PX-8 RS-232-c port (actually a 8251A) requires the proper logic level on the PIN pin, that could be provided by the UD-80-OUT pin. On the current board, the traces to the DE-9 has connected POUT to PIN.
DE-9 UD-80 header name and direction 1 ---------+ 2 ----- 1 | PX-Tx > UD-Rx 3 ----- 2 | PX-Rx < UD-Tx 4 ---------+ 5 ----- 3 | GND 6 ---------+ 7 ----+ 8 ----+ 9The pins 1, 4, 6 are shorted, as are 7 and 8.
The 9-pin DE-9 is my preferred connector as it is more universal, easier to solder and more robust than the mini-DINs.
The connection between the PX-8 and the UD-80 uses 4800 Baud, 8 bits, two stop bits. This is the standard for the PX-8 RS-232-C port. The Baud rate on the UD-80 side seems fixed, changing the remaining DIP-switches has no effect.
The replica also works with the ud80_rom7_11A ROM, but the PX-4 driver didn't redirect properly to the external screen. Will check that later. Here the files sent in FILINK mode, for the PX-8 and PX-4.
Exchanging almost any other chip on the board, the EPROM became the major suspect. Flip one pin out of the socket and connect it to the scope,. It showed some noise, but always logically low. The programmer confirmed; any address was 00h. Might have happened with the /PGM tied to low. So you can program/kill a Nec D27128D without the programming voltage.
A new EPROM programmed and inserted and there is the prompt again. The screen was too high for the display. Time to fiddle the dipswitches (UD80_rom5_21 ROM):
1. off = 80 char./line, on = 40 char./line
2.
3. off = high screen, on = normal screen
4. off = white on black, on = black on white
5.
6.
7.
8.
Connecting to the PX-8 and starting FILINK there didn't work (RS232c line not ready message), I tested both the DTE and DCE wiring. There might be a missing control like like DTR (data terminal ready) for the PX-8. It is now just a 3-wire connection. But connecting it to the PC did work before as well as did the PX-8-PC FILINK connection. Connecting the UD-80 to the PC, start filink there and press the /INT button... And there it says receiving. As expected, two files; ud80-dr.vcom and wsx.com (how the first became ud80-dr.vcom instead of ud80-drv.com) is unclear, but internally it looks like a driver (disassembly planned later).
Note the PC serial port has to be set in the proper mode and redirecting filink to an other port is a bit of old unix/Linux lore:
stty -F /dev/ttyUSB0 cs8 -cstopb -parenb speed 4800 > /dev/null ./filink > /dev/ttyUSB0 < /dev/ttyUSB0
Now the task is to prepare a proper cable for the PX-8.
As the board looks now. The new reset button (behind the blue wire)
is handy for testing DIP-switches. The original button (now INT) triggers FILINK mode.
Finally the complete board was tested with all components in place. Then it took several modifications and tests before it produced something like a video signal. Still then the signal isn't close enough to the standard for modern flat-screen displays. Old CRT based analog displays do work.
Working, somewhat.
This lasted some hours and then it just stopped working again. I learned somewhat more on how it actually works, and what some of the DIP-switches do. The last, on pin P17, but numbered 1 on the board, inverts the video to black on white.
The LEDs on the serial line, added to create some nice blinking lights when in operation, did work as a startup flag. This indicated the 6803 kept restarting. The screen is either blank and inverted or shows columns of random characters, some blinking (blinking is an attribute of the EF9346, but there are some characters that blink at an other rate, but only when the 6803 isn't in reset. This suggests the 6803 is accessing the RAM, via the EF9345.
There were more errors, and some not ready found and fixed. Some of the fixed ones:
While it worked, I had a PC connected to the serial port at 4800 Baud, and when fed characters (Enter would do) it produced this blurb:
UD-80 Plus Display Controller
=============================
Oval Automation Ltd., Courtwick Lane,
Littlehampton, Sussex, BN17 7PA, England
Hardware Rev. 1998.x.11 by A.S.Hardie
Firmware Rev. V5.21E by D.J.Isaaman
E (European) Version.
ROM Creation Date 3 June 1985
Self-test:
After that the send characters were echoed. This behaviour and that the default PX-8 port is the RS-232c (according to the review) led me to the conclusion the UD-80 is not an EPSP-device (for the SERIAL port), but half-a-terminal, like the STAT option.
This text is from September 2022
With clear images of the board and an image of the ROM contents available, it seemed clear that there was enough information available to make a replica. The two main chips, a Motorola MC6803 and a Thompson EF9345 are very well documented with datasheets and more important, application sheets. From this data it would be clear there was only one proper way to connect them.
The 6803 is a simplified 6801 with no internal ROM and just two modes, 2 and 3. The external EPROM indicated it ran in mode 3, extended multiplexed mode. The 74LS373 confirmed this. The EPROM had to be in the upper half of memory space to include the vector space.
The ports P10 to P17 of the 6803 were reserved for the 8 bit dip-switch
The EF9345 has its own direct connection for RAM using another 74LS373. So all main pins in the circuit are fixed.
No serious addressing decoding logic is present on board, only inverters. Lots of analog stuff but that is serious way to connect the logic chips. In the end, just one inverter is needed to make A15 a ChipSelect* for the ROM.
The analog stuff is the RS-232c converter and RGB video signal conversion. No need to reverse engineer, enough examples on the internet. A MAX232 solves half of the problem.
A disassmbly of the ROM confirmed its location is in the upper half of memory. All registers of the EF9345 in the lower half (A15 is Chip Select here too, but not inverted).
The situation is complete enough to design a first version of the board. But just soldering it together and see it work is very unlikely. After a long period of thinking (and working on other projects), the solution was to create a custom 6803 exerciser. Having done this before for a Z80 and 6809, it would allow checking the circuit board without processor. The exerciser doesn't do instructions, but just handles pins. In isolation, but also in combination. So Read and Write operations could be executed and monitored.
The Exerciser is build upon a Arduino ATMega2560. The program is trival (having most of the routines already in written and tested).
*1) But what the dip-switches do has to found out. A working configuration is known from the images. Really interpret and annotate the disassembly is (not yet) required.
The board was created in September 2022 and I figured it was too complex to assume it would work by just putting all components on the board and apply power. After all it was my own, untested speculative design.
The best I could do was try to test parts of the schematic in isolation and only then add an other part to test.
*1) Q9 to get a 512ms square wave, B#P24 to exercise pin P24,
*2) Used the "TTL voltage level probe" for this.
The fixes are colour coded and can be found in the oval80replica.0.8Fixes.txt document
Finally combined the 6803 exerciser with the UB-80 board to test the EPROM connection. It seems both are working. The dump below is part of the result of the D (dump command)
8D00: 7EBD8C3C 380820EE BD8C0D20 06200420 ~..<8. .... . . 8D10: 072005CE 8ECA2003 CE8F1CBD 8C2FC602 . .... ....../.. 8D20: BD8CCE36 84F88A07 BD8CC2CE FFFF0926 ...6...........& 8D30: FD850727 034A20F0 32BD8CC2 4F5FCE80 ...'.J .2...O_.. 8D40: 00EB0089 00088CA0 0026F6CE 9FFCE000 .........&...... 8D50: 8200E001 8200A300 2706CE8F B6BD8C2F ........'....../ 8D60: 5FD70339 20202020 20202020 20202020 _..9 8D70: 20202020 20202020 00202020 4F76616C . Oval 8D80: 2055442D 38302B20 44697370 6C617920 UD-80+ Display 8D90: 436F6E74 726F6C6C 65722056 352E3231 Controller V5.21 8DA0: 45000D20 20202020 55442D38 3020506C E.. UD-80 Pl 8DB0: 75732044 6973706C 61792043 6F6E7472 us Display Contr 8DC0: 6F6C6C65 720D2020 2020203D 3D3D3D3D oller. ===== 8DD0: 3D3D3D3D 3D3D3D3D 3D3D3D3D 3D3D3D3D ================ 8DE0: 3D3D3D3D 3D3D3D3D 0D0D4F76 616C2041 ========..Oval A 8DF0: 75746F6D 6174696F 6E204C74 642E2C20 utomation Ltd., 8E00: 436F7572 74776963 6B204C61 6E652C0D Courtwick Lane,. 8E10: 4C697474 6C656861 6D70746F 6E2C2053 Littlehampton, S 8E20: 75737365 782C2042 4E313720 3750412C ussex, BN17 7PA, 8E30: 20456E67 6C616E64 0D0D4861 72647761 England..Hardwa 8E40: 72652052 65762E20 31393938 2E782E31 re Rev. 1998.x.1 8E50: 31206279 20412E53 2E486172 6469650D 1 by A.S.Hardie. 8E60: 4669726D 77617265 20526576 2E205635 Firmware Rev. V5 8E70: 2E323145 20627920 442E4A2E 49736161 .21E by D.J.Isaa 8E80: 6D616E0D 45202845 75726F70 65616E29 man.E (European) 8E90: 20566572 73696F6E 2E0D0D52 4F4D2043 Version...ROM C 8EA0: 72656174 696F6E20 44617465 20203320 reation Date 3 8EB0: 4A756E65 20313938 350D0D53 656C662D June 1985..Self- 8EC0: 74657374 3A200D0D 0D004142 43444546 test: ....ABCDEF 8ED0: 4748494A 4B4C4D4E 4F505152 53545556 GHIJKLMNOPQRSTUV 8EE0: 5758595A 20202020 34302D43 4F4C554D WXYZ 40-COLUM 8EF0: 4E0D6162 63646566 6768696A 6B6C6D6E N.abcdefghijklmn
Further I rechecked the checks above to make sure I remembered then correctly.
The board is operated from 5 volt directly, so I can monitor the current. 79 mA seems Ok for the EPROM, MAX232 and some TTL.
Local:
External:
Last updated: 2024-03-02