MEMORY BOARD The memory-board contains the optional BASIC-ROMs (or EPROMs), dynamic memory, the BOOT-ROM and the address decoding for the programmable MEMORY MAP. Because the MEMORY MAP in the ASTER CT-80 is configurablem all memory elements can be placed in a very large range in memory. This includes all Memory-Mapped devices like Keyboard, Videomemory, Disk controller and Printer interface (for the latter only the memory location changes, not its I/O port). The board contains several latches for programming the MEMORY MAP. Also depending on a special MAP-ROM (small PROM realizing part of the decoding), the memory elements wil be placed in the MEMORY MAP. The MAP-ROM contents is described in the file MAP-ROM.txt. The board is designed to support both 16 kByte and 64 kByte or RAM by selecting jumper settings. The board consists of several sections: - ROM memory (Read Only Memory), - RAM memory (Random Access Memory), - Address decoding, - Buffers for Data, Address and Control busses. The ROM memory The ROM memory consists of two parts. The first is Z3, a 2 kByte EPROM containing the startup procedure for the Aster CT-80. This ROM is required for operation of the computer. During startup of the computer, routines in this ROM configure the Video Processor, configuration of the memory map and reading of the first sector from the disk in drive 0. The software in this sector control the final Video and Memory configuration. The ROM can be placed in three ranges of memory; From 0000h-0800h during startup, from 3000h-3800h during TRS-80 mode and from EC00h-F400h for CP/M and Viditel applications. See the description of the MEMORY MAP. The second, optional part of ROM memory consists of Z1 and Z2. These IC-sockets can use the original TRS-80 Level II ROM set or an 8 kByte (2564) and 4 kByte (2532) EPROM. The EPROMs exactly match the sokets, for the Level II ROM set, the pins 1, 2, 27, and 28 of socket Z1 should be left open. So pin 3 of the socket matches with pin 1 of the ROM. Another change for the Level II ROMs is adding a link between pin 20 and pin 21 of Z2. The original connection of pin 21 of Z2 should be broken. RAM memory The RAM consists of either eight 16 kByte (4116) or eight 64 kByte (4164) memory ICs. The default for an assembled Aster CT-80 is 64 kByte RAM. When 16 kByte RAM is used, this also requires a -12V supply. The MEMORY BOARD converts this to -5V. The 64 kByte ICs do not require a negative power supply. For a 64 kByte configuration, note the following: - the condensators C44, C45, C46, C47, C48, C49, C50 and C51 should be absent, - the voltage regulator T1 and the condensators C3, C7 and C8 should be absent, - jumpers J3 and J4 must not be present, - jumpers J1 and J2 should be in position 'a'. If the place the MEMORY BOARD before you with the text "MEMORYBOARD" in the top right corner, the "a" position is away from you, the "b" position is facing you. The address multiplexer is made of ICs Z4 and Z5. These are controlled by the MUX signal (pin 28c) generated by the processor board. Address decoding The larges part of the memory mapping is located on the MEMORY BOARD. Using three bits in the I/O range (port 0FEh) three bits are placed in register (Z26) controlling the memory configuration (see table). The actual address selection is provided by ICs Z16, Z17, Z18, Z20, Z22 and Z25. Z21 is the specially programmed PROM. Using this PROM reduces the chip overall count. This set of ICs also create various control signals like OE (pin 27a, VIDEO (pin 31a) and KBRD (pin 24c). Buffers for Data, Address and Control busses All signals entering and leaving the board are extra buffered to improve reliability. Each bus has its own set of ICs: - Data bus buffering uses Z23 and Z24, - Address bus buffering uses Z6 and Z7, - Control bus buffering uses Z17, Z19 and Z27. A BUSRQ signal to the processor results an tri-stating all CPU outputs except: - CLOCK, pin 18c, - SYSRESET, pin 30a, - I/O (FCh-FFh), pin 30c, - BUSAK, pin 21a. The RESET input remains operational. Some signals required for multiplexing the dynamic RAM are generated on the processor board. These signals are: - MREQ, pin 31c - MUX, pin 28c, - CAS, pin 27c, - RAS (=MEMRQ), pin 28a The MAP-ROM is an MMI 6331 IJ, which is similar to an N82S123N. Its capacity is 32x8 bits. Used pins (according to schema) 1, 2, 3, 10, 11, 12, 13 14 and 15. Pin 16 is Vcc, pin 8 is GND.