Z80 MICROPROCESSOR BOARD
The core of the CT-80 is the Z80 microprocessor. The processor is located on the same board as the switchable system clock. Also on this board is the generation of signals for reading and writing I/O-ports and memory, the signals required for the dynamc RAM refresh, and the decoded I/O select signal for port range FCh to FFh.
Almost all BUS sugnals are present on the MICROPROCESSOR BOARD. 

The clock signal is derived from a 16 MHz or a 14.1926 MHz crystal. The selection is based on complete TRS-80 timing compatibility with 1.774/3.548 MHz (derived from the 14.1926 MHz), or the faster 2/4 MHz (derived from 16 MHz). The faster configuration cannot read TRS-80 tapes. Fast CT-80 produced tapes are compatible with other fast CT-80's.
The crystal clock signal is divided by IC Z16 and reshaped by Z13 for a 50% duty cycle. An active pull up circuit (T1, C5, R3, R4 and R5) is used to improve the signal flanks. This to enabled the usage of higher clock frequencies.

ICs Z16 and Z11 create a switchable processor clock frequency (1.774/3.548 MHz for standard speed, 2/4 MHz for fast speed). The circuit allows arbitrary speed switching without risk for CPU-processing problems.
Switching to clock frequencies higher than 2 MHz can lead to access problems of EPROMs if these have access times of 350 ns or more. The Aster CT-80 allows copying the ROM contents to RAM at the same memory location. The program now runs from dynamic RAM with an access time of 150 ns. No wait cycles are needed for clock frequencies of up to 6 MHz.

The Reset part can be configured for a 'warm'-start (with resistor Ra installed) or a 'cold' start (with resistor Rb installed) when both the Reset keys of the keyboard pressed.
For TRS-80 like operating systems, a System reset can be generated on execution of a HALT instruction. This option can be switched on or off from software (port FEh, bit 5).

The used processor is a Z80A, or a Z80B, depending on hardware configuration. The Z80A is specified up to 4 MHz, the Z80B up to 6 MHz.

The address bus is buffered by ICs Z5, Z6 and Z7. Z5 is a latch keeping the high address lines stable during memory access. This approach is selected to guarantee the highest possible reliability.

The data bus is buffered by IC Z9, a bi-directional buffer.

The control bus includes a number of signals not generated by the Z80 CPU. For proper operation these have to be ORed with MEMRQ and IORQ respectively.

The I/O (FCh-FFh) signal is generated by IC Z10.