FLOPPY DISK CONTROLLER BOARD The 'standard' doublers had to do switching between single and double density within the address range 37ECh-37EFh because that was available on the floppy controller socket. Some doublers added the capability to switch between 5 1/4" and 8" drives (the latter required a higher clock speed). The LNDoubler manual contains a good description. Address map for Early MCP Floppy Disk Controller: 37E0h-37E3h W Motor on (pulsed by mono-stable flip-flop), bit 0-3: Drive select, bit 4: side select, bit 5: clock speed select (for 8" drives, note: not compatible with later CT-80 board). 37E4h-37E7h Cassette drive latch 37E8h-37EBh R Printer control bits, W Printer data latch and strobe. 37ECh-37EFh RW Floppy Disk Controller registers. The later Aster CT-80 Floppy Disk Controller integrated the double density controller into the main board. This allowed for more 'optimisations': 37E0h-37E3h W Motor on (pulsed by mono-stable flip-flop), bit 0-3: Drive select, (a jumper can move the side select to pin 4. Normally drive 3 select) bit 4: side select, bit 5: FDC select (for SD/DD), bit 6: clock speed select (for 8" drives), bit 7: select 37ECh (standard Percom) or 37E0h (special Aster) presets. 37E0h-37E3h R Reset Real Time Clock interrupt, bit 6: FDC interrupt, bit 7: RTC interrupt (40Hz). The FDC registers, both 1771 and 1791 are (between brackets the standard doubler logic): 37ECh R Status Register 37ECh W Command Register (writing FEh selects single density, writing FFh selects double density) 37EDh RW Track Register 37EEh RW Sector Register (writing C0h selects 8" disk drive, writing A0h selects 5 1/4" disk drive. This selects a higher FDC clock frequency for 8".)) 37EFh RW Data Register The standard (Percom et al.) configuration with just the bits: Address selection for density: /A0 * /A1 * /D3 * /D4 * /D5 * /D6 * /D7 * /Wr The address range for the FDCs is 37ECh-37EFh, so '/A0 * /A1' means 37ECh. The bit pattern '/D3 * /D4 * /D5 * /D6 * /D7' make sure it won't interfere with any real sector number. The /Wr makes it Write Only. On this address, /D0 is written to the flip-flop. The Q output goes to both /ChipSelect and /DDEN of the 1791, the /Q goes to the /ChipSelect of the 1771. The bit pattern 11111xx0b selects Single Density The bit pattern 11111xx1b selects Double Density To summarize, below is how the Aster CT-80 FDC board probably evolved: - At first, the Model 1 Expansion Interface was just for Single Density floppy disks. Here writing to address 37E0h-37E3h (any value) enabled the Motor On for a few seconds. Bits 0, 1, 2, 3 ware used to select drive 0, 1, 2, 3. The standard Radio Shack TRS-80 drives are single sided. - Third party DOSses added support for Double Sided drives and used bit 3 for this, limiting the maximum number of drives to 3. - Later Double Density adapters (Doublers) were developed, but these changed only the usage of address 37ECh-37EFh by using unused bits of the FDC registers. Most Doublers (but not the Radio Shack Doubler) copied the Percom Doubler usage of 37EEh bits (upper nibble) to select density (and optionally FDC clock speed for 8" disks). - Aster created an early Floppy Disk controller moving drive select to bit 4, allowing four double sided drives. Bit 5 is used to select the clock speed for the FDC (the controller was just single density, so this was for 8" disk drives). This bit didn't change CPU clock speed. (A high CPU clock might be necessary for 8" disks, but this is controlled with I/O-port FEh on the CPU board.) - The newer CT-80 FDC board used address 37E0h bit 6 to duplicate the density switch from 37EEh. Bit 7 is used to select either the standard Doubler 37ECh/37EEh high bits or the Aster special 37E0h bits (5, 6). Hardware The FLOPPY DISK CONTROLLER BOARD uses two 74LS471 256x8 3-state PROMS for address decoding.The 74LS741 is superceded by TBP28L22. My board has MMI 6309-IN chips. P.S. Somewhat related; this is what the TRS-80 Model 1 (and presumably the Aster boot ROM) does at startup with an E.I. connected and a bootable disk mounted: read 37ECh check bit 1: (if 1, E.I. present) write 37E1h, 1 (select drive 0) write 37ECh, 3 (select track 0) check 37ECh, 0 (if true, Disk drive ready) write 37EEh, 0 (select sector 0) write 37ECh, 8Ch (read command) loop: check 37ECh, 1 (if 1, data ready, if not jp loop) read 37EFh, write to 4200h++ if not 256 bytes read, jp loop (the routine might even read until the FDC signals no DRQ). jp 4200h Dump PROM1 "FDC selector" Input lines ADA to ADH are address lines A0 to A7, output lines O1 to O8 are data lines D0 to D7. Format is Intel-HEX, with added spaces. Fields: ':', size, start address, record type, data, checksum. Used part: :08 0000 00 FDFEFFFFFFFEFFFF 04 :08 0008 00 FFFEFFFFFFFEFFFF FA :08 0010 00 FFFEFFFFFFFEFFFF F2 :08 0018 00 FFFEFFFFFFFEFFFF EA :08 0020 00 FFFEFFFFFFFEFFFF E2 :08 0028 00 FFFEFFFFFFFEFFFF DA :08 0030 00 FFFEFFFFFFFEFFFF D2 :08 0038 00 FFFEFFFFFFFEFFFF CA Unused part: :08 0040 00 FFFFFFFFFFFFFFFF C0 :08 0048 00 FFFFFFFFFFFFFFFF B8 :08 0050 00 FFFFFFFFFFFFFFFF B0 :08 0058 00 FFFFFFFFFFFFFFFF A8 :08 0060 00 FFFFFFFFFFFFFFFF A0 :08 0068 00 FFFFFFFFFFFFFFFF 98 :08 0070 00 FFFFFFFFFFFFFFFF 90 :08 0078 00 FFFFFFFFFFFFFFFF 88 :08 0080 00 FFFFFFFFFFFFFFFF 80 :08 0088 00 FFFFFFFFFFFFFFFF 78 :08 0090 00 FFFFFFFFFFFFFFFF 70 :08 0098 00 FFFFFFFFFFFFFFFF 68 :08 00A0 00 FFFFFFFFFFFFFFFF 60 :08 00A8 00 FFFFFFFFFFFFFFFF 58 :08 00B0 00 FFFFFFFFFFFFFFFF 50 :08 00B8 00 FFFFFFFFFFFFFFFF 48 :08 00C0 00 FFFFFFFFFFFFFFFF 40 :08 00C8 00 FFFFFFFFFFFFFFFF 38 :08 00D0 00 FFFFFFFFFFFFFFFF 30 :08 00D8 00 FFFFFFFFFFFFFFFF 28 :08 00E0 00 FFFFFFFFFFFFFFFF 20 :08 00E8 00 FFFFFFFFFFFFFFFF 18 :08 00F0 00 FFFFFFFFFFFFFFFF 10 :08 00F8 00 FFFFFFFFFFFFFFFF 08 :00 0000 01 FF PROM1 addresses with non-FFh in HEX: BIN, actual value HEX: BIN, data bits cleared 00: 0000 0000 - FD: 1111 1101 - bit 1 01: 0000 0001 - FE: 1111 1110 - bit 0 05: 0000 0101 - FE: 1111 1110 - bit 0 09: 0000 1001 - FE: 1111 1110 - bit 0 0D: 0000 1101 - FE: 1111 1110 - bit 0 11: 0001 0001 - FE: 1111 1110 - bit 0 15: 0001 0101 - FE: 1111 1110 - bit 0 19: 0001 1001 - FE: 1111 1110 - bit 0 1D: 0001 1101 - FE: 1111 1110 - bit 0 21: 0010 0001 - FE: 1111 1110 - bit 0 25: 0010 0101 - FE: 1111 1110 - bit 0 29: 0010 1001 - FE: 1111 1110 - bit 0 2D: 0010 1101 - FE: 1111 1110 - bit 0 31: 0011 0001 - FE: 1111 1110 - bit 0 35: 0011 0101 - FE: 1111 1110 - bit 0 39: 0011 1001 - FE: 1111 1110 - bit 0 3D: 0011 1101 - FE: 1111 1110 - bit 0 Summary of addresses that clears data bits (x is don't care): SIZSEL (bit0) = /00xx xx10 /(/A1 & /A0 & D7 & /37ECh-WR) DENSSEL(bit1) = /0000 0000 /(/A1 & /A0 & /D3 & /D4 & /D5 & /D6 & /D7 & /37ECh-WR) inputs: 1034 567W AADD DDDR PROM1 "FDC selector" pin-signal names A1 1 - ADA || VCC - 20 A0 2 - ADB || ADH - 19 /37ECh-WR D3 3 - ADC || ADG - 18 D7 D4 4 - ADD || ADF - 17 D6 D5 5 - ADE || SL2 - 16 low SIZSEL 6 - DO1 || SL1 - 15 low DENSSEL 7 - DO2 || DO8 - 14 nc nc 8 - DO3 || DO7 - 13 nc nc 9 - DO4 || DO6 - 12 nc 10 - GND || DO5 - 11 nc Dump PROM2 "Address decoder" Input lines ADA to ADH are address lines A0 to A7, output lines O1 to O8 are data lines D0 to D7. Format is Intel-HEX, with added spaces. Fields: ':', size, start address, record type, data, checksum. Used part: :08 0000 00 FDBCF6FDFDFDFDFD 58 :08 0008 00 FDFDFDFDFDFDFDFD 08 :08 0010 00 FDFDFDFDFDFDFDFD 00 :08 0018 00 FDFDFDFDFDFDFDFD F8 :08 0020 00 FDFD7AFDFDFDFDFD 73 :08 0028 00 FDFDFDFDFDFDFDFD E8 :08 0030 00 FDFDFDFDFDFDFDFD E0 :08 0038 00 FDFDFDFDFDFDFDFD D8 :08 0040 00 FDFDFDFDFDFDFDFD D0 :08 0048 00 FDFDFDFDFDFDFDFD C8 :08 0050 00 FDFDFDFDFDFDFDFD C0 :08 0058 00 FDFDFDFDFDFDFDFD B8 :08 0060 00 FDECDAFDFDFDFDFD E4 :08 0068 00 FDFDFDFDFDFDFDFD A8 :08 0070 00 FDFDFDFDFDFDFDFD A0 :08 0078 00 FDFDFDFDFDFDFDFD 98 Unused part: :08 0080 00 FFFFFFFFFFFFFFFF 80 :08 0088 00 FFFFFFFFFFFFFFFF 78 :08 0090 00 FFFFFFFFFFFFFFFF 70 :08 0098 00 FFFFFFFFFFFFFFFF 68 :08 00A0 00 FFFFFFFFFFFFFFFF 60 :08 00A8 00 FFFFFFFFFFFFFFFF 58 :08 00B0 00 FFFFFFFFFFFFFFFF 50 :08 00B8 00 FFFFFFFFFFFFFFFF 48 :08 00C0 00 FFFFFFFFFFFFFFFF 40 :08 00C8 00 FFFFFFFFFFFFFFFF 38 :08 00D0 00 FFFFFFFFFFFFFFFF 30 :08 00D8 00 FFFFFFFFFFFFFFFF 28 :08 00E0 00 FFFFFFFFFFFFFFFF 20 :08 00E8 00 FFFFFFFFFFFFFFFF 18 :08 00F0 00 FFFFFFFFFFFFFFFF 10 :08 00F8 00 FFFFFFFFFFFFFFFF 08 :00 0000 01 FF PROM2 addresses with non-FFh in HEX: BIN - actual value HEX: BIN - data bits cleared: 0xxx xxxx: FD (1111 1101) bit 1 01: 0000 0001 - BC: 1011 1100 - bit 0, 1, 6 02: 0000 0010 - F6: 1111 0110 - bit 0, 3 22: 0010 0010 - 7A: 0111 1010 - bit 0, 2, 7 61: 0110 0001 - EC: 1110 1100 - bit 0, 1, 4 62: 0110 0010 - DA: 1101 1010 - bit 0, 2, 5 Summary of addresses in binary that clears data bits (x is don't care): prompin: HGFE DCBA HGFE DCBA HGFE DCBA HGFE DCBA HGFE DCBA bit0 = /(0000 0001 or 0000 0010 or 0010 0010 or 0110 0001 or 0110 0010) /RAMDIS bit1 = /(0000 0001 or 0110 0001) /D4-D7-WR 37E0-37E3h + 37EC-37EFh bit2 = /(0010 0010 or 0110 0010) /D4-D7-RD 37E0-37E3h + 37EC-37EFh bit3 = /(0000 0010) /D6-D7-RD 37E0-37E3h bit4 = /(0110 0001) /FDC_WR 37EC-37EFh bit5 = /(0110 0010) /FCD_RD 37EC-37EFh bit6 = /(0000 0001) /DRIVE_SEL 37E0-37E3h bit7 = /(0010 0010) /DIP_SEL_RD 37E4-37E7h inputs: 032A E4WR PROM2 "Address decoder" ' name abbr. pinno. - prompin || prompin - pinno. abbr. pin-signal name ' /RD R 1 - ADA || VCC - 20 /WR W 2 - ADB || ADH - 19 0 low BA4 4 3 - ADC || ADG - 18 3 BA3 /OE E 4 - ADD || ADF - 17 2 BA2 A5-A10 A 5 - ADE || SL2 - 16 low /RAMDIS 6 - DO0 || SL1 - 15 low /D4-D7-WR 7 - DO1 || DO7 - 14 /DIP_SEL 37E4h /D4-D7-RD 8 - DO2 || DO6 - 13 /DRIVE_SEL 37E0h /D6-D7-RD 9 - DO3 || DO5 - 12 /FCD_RD 37ECh 10 - GND || DO4 - 11 /FDC_WR 37ECh /OE = ? /A15 & /A14 & A13 & A12 & A11 ? (from Memory bord) A5-A10 = /(A5 & A6 & A7 & A8 & A9 & A10) bin: xxxx x111 111x xxxx 37E0-37E3h: 0011 0111 1110 00xx Drive & side select, Motor On (WR) 37E4-37E7h: 0011 0111 1110 01xx Cassette drive latch (WR), DIP switches (RD) 37E8-37EBh: 0011 0111 1110 10xx Printer control 37EC-37EFh: 0011 0111 1110 11xx FDC registers (RD/WR) + Density and Drive size select (WR)