D-RAM Test ROM, to be installed in the O.S. socket, 2A.
There are two jumpers close to the socket J4 and J5, but
they are not related to the O.S. ROM.

Output:

PX-8,HC-80/88 D-RAM Test Program
            Ver. 1.0

          Bit 76543210
        1 :   ........
        2 :   ........
        3 :   ........
        ....

( I stopped it at 101.)

This Test ROM relies on the 8251 USART to be working and reports
its progress on the RS232C port, 4800 Bd, 8N1. I used a #724 type
cable. No output is generated for the LCD screen. Each test run takes
about 43 seconds. It might be intended as an indefinite burn-in test.
At the first run the keyboard LEDs are on, for later runs they are off.

The program code first test the upper half of RAM running from ROM,
then copies (part of) itself to RAM to test the lower half of RAM.
The program does not rely on RAM for its status, all is kept in the
registers.

Reporting includes defective bits in the RAM I.C. on the PCB.
PX-8: 5D 7E 4E 6D 5E 6E 4D 7D
PX-4: 4C 4D 5C 5D 6C 6D 7D 7C
(can't show this as no bits failed)

The checksum for the ROM that my programmer reports is 5B8AF1. The
handwritten label on my 'original' is "MapPin Ram Test V.10".

F.J.Kraan, 2023-05-01