Epson created several RAM Disk units for the PX-8 and PX-4. For the PX-8 the original is a 60 kByte and a 120 kByte RAM Disk. These are so called 'Intelligent' as there is a Z80 processor with firmware which handles request from the PX-8. This is the RAM Disk variant mentioned in the User Manual and Technical Manual. The 'Intelligent' RAM Disk uses I/O ports 80h and 81h.
The Operating System Reference Manual also has info on the 'Non-Intelligent' RAM Disk. These devices didn't exist as stand-alone device but were combined with other devices like the 'Japanese-language processing unit', ROM capsules, direct modem or the 'Synchronous communication unit'. The 'Non-Intelligent' RAM Disk is I/O mapped, and uses ports to specify the address and read/write data. One extra port is used for the Command/Status registers. One extra feature makes this device not trival to recreate; the lower address byte is self- incrementing, after each read or write the value is incremented. So each successive data read/write will use the next memory location. This allows for fast reading and writing (Z80 processor OTIR and INIR instructions). The 'Non-Intelligent' RAM Disk uses I/O ports 90h to 94h.
For the PX-4 there appears to be only a RAM Disk of the 'Non-Intelligent' type. It is combined with the 64k-bit to 1-Mbit ROM capsule. The port usage is the same as for the PX-8. The addressing space, accessed with the three address registers, is divided between RAM (00000h-1FFFFh) and ROM (20000h-3FFFFh). The ROM capsule is not checked or managed by the O.S. but needs user software.
It is notable all Epson made RAM Disks use dynamic RAM, probablty the most economic option in the 1980s. It is nice that there are better options now. The board has a simple provision to attach a 3V battery, making the RAM contents persistant. A more reliable solution is replacing the SRAM with a DS1245Y persistent RAM device or an STK14CA8C based module.
Why the 120 kByte, while the memory is 128 kByte? The driver for the RAM disk reserves a section of memory for checksums for each page of memory. With each write operation the corresponding checksum is updated. At startup, all checksums are checked and when one fails, the computer suggests a format as is sees the RAM disk as corrupted (or uninitialized). The RAM disk is logically seen as a disk with 15 tracks and 64 sectors per track.
These are the interesting parts of the RAM Disk hardware:
The Addrdec GAL is mainly an address decoder with a timing signal generator on the spare pins.
The Rincrementer GAL has two modes; loading a new value in the registers and increment the eight bits. The difference is made by the level of the /LOAD signal at the rising edge of the clock. The loading of a new value is triggered by the /WLOAD (not-Write LOw ADdress byte). /WLOAD is extended by an SR-flipflop and the end is the /M1 of the next instruction. The other signal is the /DATCS siglal used to read and write a byte from the RAM. The address should be stable at the rising edge of the /RD or /WR signal. Here the best option seems to be a delay the GAL CLK signal. An SR-flipflop generates the /DlyDATCS from /DATCS. Some spare pins and gates of the AddressDecoder GAL combine the normal /WLOAD clock with the extended /DATCS clock. They both end with the falling edge of /M1, so will not interfere with the CPU data transfers (occurring at 'M2' and up).
The image below shows the various signal timings made with PulseView/sigrok. It also shows the very cool Z80 signal interpreter.
The alogorithm to properly increment eight bits is surprisingly simple:
The pulse extenders use a basic SR-flipflop.
| with PX-8 |  |
Here the RAM Disk connected to the PX-4. The flatcable used is the Epson standard #727,
a 50-wire two header flatcable. The PX-8 connection is a bit awkward, but the advantage (for me) is creating one board for both the PX-8 and PX-4. The busses are logically equivalent, but have a different pinout. Note the flatcable headers used with the PX8 (and PX-4) have two out-of-center notches, instead of the more usual single center notch. If your header has a notch, you have to cut or grind it off. The unified board and case doesn't work very well here because nearby connectors are blocked. These are the RS-232c on one side and the BCR on the other side. So a new board acnd case will be designed for just the PX-8. The old board might still work with the wedge construction of the original PX-8 RAM disk, but that is too complicated, or a exercise for the constructive reader. |
| with PX-4 |   |
Here the RAM Disk connected to the PX-4. There is a base below the RAM disk board,
but the upper case is not tested yet. As pictured, there is no battery connected, the 120k RAM disk is not saved between power cycles. Batteries can be as simple as two AA cells in a clip, or a CR2032 cell. The angled header is composed of a 40 pin and a 10 pin, as I couldn't find a 50 pin version. The case works very well for the PX-4. This part is completed. The case is a bit high for just the base board, even with a small battery, but with the expansion board this space is useful. |
| Extension board |
 |
The extension connector allows three more 128 kByte SRAMs to be connected. The CP/M in the PX-4 and
PX-8 does not support this, but it was easy to adds some more lines to the upper address register.
At least the PX-4 supports an 128 kByte ROM in part this address range. The board is as yet vaporware... |
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Updated: 2026-02-28