Based on P800M Instruction Set (Extended Specification) Pub No. 5122 991 27366, January 1982 and P856M/P857M System Handbook, Pub No. 5122 991 26932, April 1976, ch. 7. This list excludes the P857M specific Floating-Point instructions. r1, r2, r3 - k - constant (8-bit) lk - long constant (16-bit) m - memory location cnd - condition n - bit positions addr - memory location D - 2nd instruction word value Condition codes 'cnd' (bits 10,9,8): G - greater than xx1 L - less than x1x Z - zero 1xx NZ - Not Zero 0xx EQ - Equal 1xx NE - Not Equal 0xx 7 111 Operand type T1 Register/Register - Format 1 (short) The operand is the value in the register specified by R2 of the instruction format. T2 Long Constant - Format 1 (long) R2 == 0 The operand is the value in the least significant word, all sixteen bits, of the double length instruction format. T3 Address in Register - Format 1 (short) R2 <> 0, Address in R2 The operand is held in memory. The memory address of the operand is the value in the register specified by R2 of the instruction format. T4 Address in Next Word - Format 1 (long) R2 == 0, Address in next word The operand is held in memory. The memory address of the operand is the value in the least significant word of the double length instruction. T5 Indexed Address in Next Word - Format 1 (long) R2 <> 0, Indexed The operand is held in memory. The memory address of the operand is found by adding the value in the register specified by R2 of the instruction format to the value in the least significant word of the double length instruction. T6 Indirect Address in Next Word - Format 1 (long) R2 == 0, Indirect The operand is held in memory. The memory address of the operand is also held in memory. This indirect address is the value in the least significant word of the double length instruction. T7 Indexed Indirect Address in Next Word - Format 1 (long) R2 <> 0, Indexed indirect The operand is held in memory. The memory address of the operand is also held in memory. This indirect address is found by adding the value in the register specified by R2 of the instruction format to the value in the least significant word of the double length instruction. T8 Short Constant - Format 0 The operand is the value in the least significant eight bits of the instruction format. instr. description syntax type page AB Absolute conditional branch AB [cnd] k T8 1.085 ABI Absolute branch indirect ABI cnd[*] m [,r2] T4 - T7 1.087 ABL Absolute conditional branch long ABL [cnd] lk T2 1.085 ABR Absolute branch to register ABR cnd[*] r2 T1, T3 1.086 AD Addition AD[*] r1, m [,r2] T4 - T7 1.023 ADK Add constant ADK r3, k T8 1.021 ADKL Add constant long ADK r1, lk T2 1.021 ADR Addition register/register ADR[*] r1, r2 T1, T3 1.022 ADRS Addition register/register ADRS r1, r2 T3 1.022 ADS Addition ADS[*] r1, m [,r2] T4 - T7 1.023 ANK Logical and with constant ANK r3, k T8 1.061 ANKL Logical and with constant long ANKL r1, lk T2 1.061 AN Logical AND AN[*] r1, m [,r2] T4 - T7 1.063 ANR Logical AND register/register ANR[*] r1, r2 T1, T3 1.062 ANRS Logical AND register/register ANRS r1, r2 T3 1.062 ANS Logical AND ANS[*] r1, m [,r2] T4 - T7 1.063 C1 Ones complement C1[*] r1, m [,r2] T4 - T7 1.032 C1R Ones complement register/register C1R[*] r1, r2 T1, T3 1.033 C1RS Ones complement register/register C1RS r2 T3 1.033 C1S Ones complement C1S[*] m [,r2] T4 - T7 1.032 C2R Twos complement register/register C2R r2 T3 1.035 C2 Twos complement C2[*] m [,r2] T4 - T7 1.036 CC Compare characters CC[*] r1, m [,r2] T4 - T7 1.081 CCK Compare character with constant CCK r1, lk T2 1.079 CCR Compare character/register CCR r1, r2 T3 1.080 CF Call function CF r1, lk T2 1.090 CFI Call function indirect CFI[*] r1, m [,r2] T4 - T7 1.092 CFR Call function register CFR[*] r1, r2 T1, T3 1.091 CIO Control Input/Output CIO T8 1.137 CM Clear memory CM[*] m [,r2] T4 - T7 1.038 CMR Clear memory/register CMR r2 T3 1.037 CW Compare words CW[*] r1, m [,r2] T4 - T7 1.031 CWK Compare word with constant CWK r1, lk T2 1.029 CWR Compare words register/register CWR[*] r1, r2 T1, T3 1.030 DA Double add DA[*] m [,r2] T4 - T7 1.047 DAK Double add with constant DAK lk1, lk2 T2 1.045 DAR Double add register/register DAR[*] r2 T1, T3 1.046 DLA Double left and arithmetic shift DLA n T8 1.107 DLC Double left and circular shift DLC n T8 1.111 DLL Double left and logical shift DLL n T8 1.109 DLN Double left and normalize shift DLN r2 T8 1.113 DRA Double right and arithmetic shift DRA n T8 1.108 DRC Double right and circular shift DRC n T8 1.112 DRL Double right and logical shift DRL n T8 1.110 DRN Double right and normalize shift DRN r2 T8 1.114 DS Double subtract DS[*] m [,r2] T4 - T7 1.050 DSK Double subtract with constant DSK lk1, lk2 T2 1.048 DSR Double subtract register/register DSR[*] r2 T1, T3 1.049 DV Divide DV[*] m [,r2] T4 - T7 1.044 DVK Divide by constant DVK lk T2 1.042 DVR Divide register/register DVR[*] r2 T1, T3 1.043 ENB Enable ENB T8 1-134 ECR Exchange characters register/register ECR r1, r2 T1 1.073 EL Extended Load (MMU) EL T4 - T7 1.017 ELR Extended Load Register (MMU) ELR T3 1.018 ES Extended Store (MMU) ES T4 - T7 1.019 ESR Extended Store Register (MMU) ESR T3 1.020 EX Execute EX[*] m [,r2] T4 - T7 1.097 EXK Execute constant EXK lk T2 1.096 EXR Execute register EXR[*] r2 T1, T3 1.095 HLT Halt HLT T8 1-132 INH Inhibit Interrupt INH T8 1-133 IM Increment memory IM[*] m [,r2] T4 - T7 1.025 IMR Increment memory/register IMR r2 T3 1.024 INR Input to Register INR T8 1.143 LC Load character LC[*] r1, m [,r2] T4 - T7 1.076 LCK Load character with constant LCK r1, lk T2 1.074 LCR Load character/register LCR r1, r2 T3 1.075 LD Load Register LD[*] r1, m [,r2] T4 - T7 1.007 LDA Load address LDA r1, D, r2 T1 1.020A LDKL Load constant long LDKL r1, lk T2 1.009 LDK Load constant LDK r3, k T8 1.009 LDR Load register/register LDR[*] r1, r2 T1, T3 1.008 LKM Link To Monitor LKM T8 1-135 MLK Multiple load constant MLK n T2 1.013 ML Multiple load ML[*] n, m [,r2] T4 - T7 1.012 MLR Multiple load/register MLR n, r2 T3 1.014 MS Multiple store MS[*] n, m [,r2] T4 - T7 1.015 MSR Multiple store register MSR n, r2 T3 1.016 MUK Multiply with constant MUK lk T2 1.039 MU Multiply MU[*] m [,r2] T4 - T7 1.041 MUR Multiply register/register MUR[*] r2 T1, T3 1.040 NGR Negate register NGR r1, r2 T1 1.034 ORK Logical OR with constant ORK r3, k T8 1.064 ORKL Logical OR with constant long ORKL r1, lk T2 1.064 OR Logical OR OR r1, m [,r2] T4 - T7 1.066 ORR Logical OR register/register ORR[*] r1, r2 T1, T3 1.065 ORRS Logical OR register/register ORRS r1, r2 T3 1.065 ORS Logical OR ORS[*] r1, m [,r2] T4 - T7 0.066 OTR Output from Register OTR T8 1.144 RB Relative backwards conditional branch RB [cnd] m T8 1.089 RER Read external register RER r3, addr T8 1.121 RF Relative forward conditional branch RF [cnd] m T8 1.088 RIT Reset Internal Interrupt RIT T8 1-136 RTN Return from function (A0-14) RTN r2 T3 1.093 RTN Return from function (A15) RTN A15 T3 1.093 SC Store character SC[*] r1, m [,r2] T4 - T7 1.078 SCR Store character/register SCR r1, r2 T3 1.077 SLA Single left and arithmetic shift SLA r3, n T8 1-099 SLC Single left and circular shift SLC r3, n T8 1.103 SLL Single left and logical shift SSL r3, n T8 1.101 SLN Single left and normalize shift SLN r3, r2 T8 1.105 SMD Set Mode SMD T8 1-137 SRA Single right and arithmetic shift SRA r3, n T8 1.100 SRC Single right and circular shift SRC r3, n T8 1.104 SRL Single right and logical shift SRL r3, n T8 1.102 SRN Single right and normalize shift SRN r3, r2 T8 1.106 SST Send Status SST T8 1.145 STR Store register/register STR r1,r2 T3 1.011 ST Store register ST[*] r1, m [,r2] T4 - T7 1.010 SU Subtract word SU[*] r1, m [,r2] T4 - T7 1.028 SUK Subtract constant SUK r3, k T8 1.026 SUKL Subtract constant long SUKL r1, lk T2 1.027 SURS Subtract register/register SURS r1, r2 T3 1.026 SUR Subtract register/register SUR[*] r1, r2 T1, T3 1.027 SUS Subtract word SUS[*] r1, m [,r2] T4 - T7 1.028 TBR Test Bit/Register TBR r2 T3 1.072E TB Test Bit TB[*] m [,r2] T4 - T7 1.072D TM Test mask TM r1, r2 T1 1.070 TNM Test not mask TNM r1, r2 T1 1.071 TRBR Test and Reset Bit/Register TRBR r2 T3 1.072C TRB Test and Reset Bit TRB[*] m [,r2] T4 - T7 1.072B TSBR Test and Set Bit/Register TSBR r2 T3 1.072A TSB Test and Set Bit TSB[*] m [,r2] T4 - T7 1.072 TST Test Status TST T8 1.148 WER Write external register WER r3, addr T8 1.119 XR Exclusive OR XR[*] r1, m [,r2] T4 - T7 1.068 XRK Exclusive OR with constant XRK r3, k T8 1.067 XRKL Exclusive OR with constant long XRKL r1, lk T2 1.067 XRR Exclusive OR register/register XRR[*] r1, r2 T1, T3 1.069 XRS Exclusive OR XRS[*] r1, m [,r2] T1, T3 1.068 XRRS Exclusive OR register/register XRRS r1, r2 T3 1.069 Latest update: 2025-11-18